Development of Low Power Test Data Compression Techniques for Digital VLSI Circuits

Optimization Techniques for Low Power VLSI Circuits

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

Low Power Techniques for Digital GaAs VLSI

This paper presents a survey of low-power digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems and proposes new design concepts in methodology and architecture based on implementation of Pseudo-Dynamic Latched Logic in order to achieve reasonable power-delay-area tradeoff The approach is highly suitable for self-timed systems where the complexities of clock sk...

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Glitch Power Minimization Techniques in Low Power VLSI Circuits

Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is...

Emerging Power-Gating Techniques for Low Power Digital Circuits